Ïðèìå÷àíèå: "*" - âñå èëè áîëüøàÿ ÷àñòü ñîäåðæèìîãî ïîéäåò íà ëþáîì CP/M-ñîâìåñòèìîì êîìïüþòåðå.

Ïîä "ATM3" â îáîçíà÷åíèè òèïà êîìïüþòåðà ïîäðàçóìåâàåòñÿ ZX-Evolution/BaseConf.

Vec-643 -

If you want, I can:

| Phase | Duration | Key Deliverables | |-------|----------|------------------| | | 1 wk | – Architecture approval (PM, SC) – Baseline metrics captured (latency, CPU load) | | Phase 1 – Scheduler Integration | 2 wks | – FreeRTOS port merged – Task skeletons implemented | | Phase 2 – CAN Driver Refactor | 2 wks | – ISR → Queue driver – Unit tests & static analysis | | Phase 3 – Dual‑Core Partitioning | 1 wk | – Core‑1 services migrated – Inter‑core communication validated | | Phase 4 – Safety & Timing Re‑analysis | 1 wk | – WCET report – Updated safety case | | Phase 5 – Verification & Validation | 2 wks | – HIL stress tests – NVH on‑track validation – Regression suite pass | | Phase 6 – Documentation & Release | 1 wk | – Updated design docs, release notes – Training for field service engineers | | Total | 10 weeks | | VEC-643

– The VEC firmware uses a blocking while (!msgReady) construct that prevents the scheduler from pre‑empting the loop, and the CAN driver runs in interrupt‑latency mode without proper priority inversion handling. If you want, I can: | Phase |

[Today's Date]